Levels of Representation of Programs and the Architecture of Universal Host Machines

Coordinated Science Laboratory was formerly known as Control Systems LaboratoryJoint Services Electronics Program / DAAB-07-72-C-025

The Effect of Program Behavior Upon Interleaved Memory Bandwidth in a Multiprocessor Environment

Coordinated Science Laboratory was formerly known as Control Systems LaboratoryJoint Services Electronics Program / DAAB-07-72-C-0259Ope

Pseudo-Randomly Interleaved Memory

Interleaved memories are often used to provide the high bandwidth needed by multi- processors and high performance uniprocessors. The manner in which memory locations are distributed across the memory modules has a significant influence on whether, and for which types of reference patterns, the full bandwidth of the memory system is achieved. The most common interleaved memory architecture is the sequentially interleaved memory in which successive memory locations are assigned to successive memory modules. Although such an architecture is the simplest to implement and provides good performance with strides that are odd integers, it can degrade badly in the face of even strides, especially strides that are a power of two. This happens because all the memory references are concentrated on a subset of the memory modules. Pseudo

Embedded computing: New directions in architecture and automation

embedded computing, special-purpose architectures, customization, custom architectures, off-theshelf customizable systems, FPGA, automation, architecture synthesis, hardwaresoftware co-design, processor-compiler codesign, frameworks, constructors, constructors, design space exploration, PICO, system synthesis, VLIW synthesis, nonprogrammable accelerator synthesis, cache hierarchy synthesis With the advent of system level integration (SLI) and system-on-chip (SOC), the center of gravity of the computer industry is moving from personal computing into embedded computing. The resulting upheaval is only just beginning to be widely appreciated. The opportunities, needs and constraints of this next generation of computing are somewhat different from those to which we have got accustomed in general-purpose computing. In turn, we believe that this will lead to significantly different computer architectures, at both the system and the processor levels, and a rich diversity of off-the-shelf and custom designs. Furthermore, we predict that embedded computing will introduce a new theme into computer architecture: automation of computer architecture. In this report, we elaborate on these claims and provide, as an example, an overview of PICO, the architecture synthesis system that the authors and their colleagues have been developing over the past five years